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M ,
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P ,
Q ,
R ,
S ,
T ,
U ,
V ,
W ,
X ,
Y ,
Z ,
A
Absolute path, 461
Access control list, 468
Access token, 468
Accumulator, 18, 42, 333
ACL (see Access Control List)
Active matrix display, 95
Adaptive routing, 538
Adder, 135-137
carry select, 137
full, 136-137
half, 135-136
ripple carry, 137
Additive inverse, 351
Address, memory, 57
Address decoding, 195-197
Address space, 405
Addressing, 322
based-indexed, 338
branch instructions, 341-342
direct, 334
immediate, 334
indexed, 336-338
Addressing (continued)
ISA level, 342-347
register indirect, 335-336
register, 334-335
stack, 338-341
Addressing modes, 333-342
discussion, 347
JVM, 346-347
Pentium II, 344-346
Aggregate bandwidth, 540
Aiken, Howard, 16
Algorithm, 8
ALU (see Arithmetic Logic Unit)
Amdahl's law, 541
Amplitude modulation, 106
Analytical engine, 14
Applet, 34
Arbitration, PCI bus, 186
Architecture, 7, 44
Arithmetic, binary, 640
Arithmetic logic unit, 5, 40, 138-139, 204-209
Array processor, 53, 554-555
ASCII code, 109-110
Assembler, 7, 484, 498-506
pass one, 499-502
symbol table, 505-507
two-pass, 498-499
Assembler directive, 491
Assembly language
characteristics, 484-485
pseudoinstructions, 491-493
statements, 488-491
why use, 485-488
Assembly language level, 483-522
Assembly process, 498-506
Asserted signal, 150
Associative memory, 420-421, 505
Asynchronous bus, 160, 163-165
Asynchronous transfer mode, 596-597
Atanasoff, John, 15
ATM (see Asynchronous Transfer Mode)
Attraction memory, 585
Attribute byte, 96
Audio-visual disk drive, 72
B
Babbage, Charles, 13-14
Baby feeding algorithms, 411
Backward compatibility, 304
Ball grid array, 181
Barrier, 551, 600
Base, 118
Based-indexed addressing, 338
Basic block, 281
Basic input output system, 74
Batch system, 11
Baud, 107
BCD (see Binary Coded Decimal)
Bechtolsheim, Andy, 32
Benchmark, 486
Best fit algorithm, 420
BGA (see Ball Grid Array)
Big endian, 59
Binary arithmetic, 640
Binary coded decimal, 57
Binary number, 631-642
negative, 637-640
Binary search, 505
Binding time, 512-515
BIOS (see Basic Input Output System)
Bipolar transistor, 120
BIPUSH IJVM instruction, 222, 237
Bisection bandwidth, 532
Bit, 56-57, 634
Bit map, 320
Bit slice, 139
Bit-map terminal, 96-98
Block cache, 448
Block-level parallelism, 547
Block transfer, bus, 168
Blocking network, 573
Boole, George, 120
Boolean algebra, 120-127
Branch history shift register, 275
Branch prediction, 270-276
dynamic, 273-275
static, 275-276
Broadcasting, 550
Buffer, circular, 438
Bundle, 392
Burroughs B5000, 21
Bus, 19, 39, 89-90, 156-170
asynchronous, 163-165
block transfer, 168
EISA, 183
handshaking, 164
IBM PC, 183
ISA, 181-183
legacy, 170
multiplexed, 160
PCI, 183-189
synchronous, 160-163
USB, 189-193
Bus arbiter, 90
Bus arbitration, 165-167
PCI, 186
Bus clocking, 160-165
Bus cycle, 160
Bus driver, 158
Bus grant, 165-167
Bus master, 158
Bus operation, 167-170
Bus protocol, 157
Bus receiver, 158
Bus request, 165-167
Bus skew, 160
Bus slave, 158
Bus timing, 160-163
Bus transceiver, 158
Bus width, 159-160
Busy waiting, 357
Byron, Lord, 15
Byte ordering, 58-61
Byte, 58, 307
C
Cache coherence, 565
Cache coherent NUMA, 574, 575-585
Cache consistency, 565
Cache hit, 268
Cache line, 67, 266, 565
Cache manager, Windows NT, 452
Cache memory, 30, 65-67, 265-270
direct-mapped, 267-269
invalidate strategy, 566
level 2, 265
MESI protocol, 568-569
multiple levels, 265-266
set associative, 269-270
snooping, 564-569
split, 67, 265
unified, 67
update strategy, 566
write allocate, 270, 566
write back, 270
write deferred, 270
write once, 568
write through, 270, 565
Cache miss, 268
Cache only memory access, 553, 585-586
Call gate, 425
Carrier, 106
Carry select adder, 137
Cathode ray tube, 93
CC-NUMA (see Cache Coherent NUMA)
CD-recordable, 84-86
CD-rewritable, 86
CD-ROM, 80-83
sector, 82
track, 84
XA, 84
CDC 6600, 14, 20, 21, 52, 277, 545
Celeron, 30
Cell, memory, 57
Central processing unit, 39-56
Chaining operations, 559
Character code, 109-112
Character-map terminal, 96
Checkerboarding, 419
Child process, 470
Chip, 128
Chip, CPU, 154-156
Circuit equivalence, 123-127
Circuit switching, 536
CISC (see Complex Instruction Set Computer)
Clock, 139-141
Clock cycle time, 139
Clocked D latch, 143
Clocked SR latch, 142-143
Clone, 24
Closure, 632
Cluster, 468
Cluster of workstations, 28, 553, 592-593
Coarse-grained parallelism, 525
Code page, 111
Code point, 111
Codeword, 61
Collector, 118
Color gamut, 105
Color palette, 97
COLOSSUS, 16
COMA (see Cache Only Memory Access)
Combinational circuit, 129-134
arithmetic, 134-139
comparator, 131-132
decoder, 130-131
multiplexer, 130-131
Committed page, 457
Common buffering, 537
Communication method, 549-550
Communication models, 526-530
Communicator, 600
Comparator, 131
Comparison and branch instructions, 352-353
Comparison of architectures, 296-298
Compiler, 7, 484
Completeness property, 123
Complex instruction set computer, 46-47
Computational paradigm, 548-549
Computer architecture, 7
milestones, 13-24
Computer center, 23
Computer organization, 7
Condition codes, 310
Condition variable, 473
Conditional execution, 393
Consistency (see Memory semantics)
Consistency model, 560
Constant pool, 220
Constant pool pointer, 205, 221, 232
Context, 427
Control Data Corporation, 20-21
Control signal, 209
Control store, 45, 213
Controller, 89
Conversion between radices, 635-637
Copy on write, 456
Core dump, 10
Coroutine, 376-379
Cougar, 592
COW (see Cluster of Workstations)
CPP (see Constant Pool Pointer)
CPU (see Central Processing Unit)
CPU chip, 154-156
Cray-1, 557-559
Cray, Seymour, 20-21
Cray T3E, 589-590
CRC (see Cyclic Redundancy Code)
Critical section, 476
Crossbar switch, 569
Crosspoint, 570
CRT (see Cathode Ray Tube)
Cube network, 534
Cycle stealing, 90, 359
Cyclic redundancy code, 193
Cylinder, 71
CYMK printer, 104
D
D latch, 143
Daisy chaining, 165-167
DAS (see Distributed ASCI Supercomputer)
DASH multiprocessor, 577-580
Data movement instruction, 348-349
Data path, 6, 40, 204-210
Mic-1, 214
Mic-2, 252
Mic-3, 256
Mic-4, 261
timing, 207-209
Data path cycle, 41
Data pump, 582
Data types
nonnumeric, 319-321
numeric, 319-321
Deadlock, 538
DEC PDP-1, 19
DEC PDP-8, 19
DEC VAX, 45, 46
Decoder, 130
Decoding unit, 261
Degree, 532
Delay slot, 272
Demand paging, 409-412
De Morgan's law, 125-126
Demultiplexer, 130
Denormalized number, 649
Design principles, RISC, 47-49
Device driver, Windows NT, 452
Device level, 5, 118
Diameter, network, 532
Dibit modulation, 107
Difference engine, 13
Digital Equipment Corporation, 14, 19, 45
Digital logic level, 5, 117-202
Digital versatile disk, 86-88
Dimensional routing, 538
Dimensionality, 533
DIMM (see Dual Inline Memory Module)
DIP (see Dual Inline Package)
Direct addressing, 334
Direct memory access, 90, 358
Direct-mapped cache, 267-269
Directory, 435
Directory architecture for shared memory,
Directory management, 435-436
Directory-based multiprocessor, 575-585
Disk, 68-88
audio-visual, 72
CD-ROM, 80-83
DVD, 86-88
IDE, 73-75
Disk (continued)
magnetic, 70-80
optical, 80-88
RAID, 76-80
SCSI, 75-76
Winchester, 71
Disk controller, 73
Diskette, 73
Dispatch/execute unit, Pentium II, 285-286
Distributed ASCI Supercomputer, 593
Distributed memory system, 529, 602-604
hardware, 574
Divide and conquer algorithm, 548
DLL (see Dynamic Link Library)
DMA (see Direct Memory Access)
Dots per inch, 102
Double indirect block, 464
Double precision number, 318
Double torus network, 534
DPI (see Dots Per Inch)
DRAM (see Dynamic RAM)
Dribbling, 293
DSM (see Distributed Shared Memory)
Dual inline memory module, 68
Dual inline package, 128
DUP IJVM instruction, 222, 223, 237
DVD (see Digital Versatile Disk)
Dyadic instructions, 349-350
Dye-based ink, 105
Dye-sublimation printer, 106
Dynamic link library, 517-518
Dynamic linking, 515
Dynamic RAM, 152, 154
Dynamic relocation, 512-515
E
E-register, 589
Eagle, 591
Eckert, J. Presper, 17
ECL (see Emitter Coupled Logic)
Edge triggered versus level triggered, 144
EDO memory (see Extended Data
Output memory)
EDVAC, 17
EEPROM (see Electrically Erasable PROM)
EIDE (see Extended IDE)
EISA bus (See Extended ISA bus)
Emitter, 118
Emitter coupled logic, 120
Enable, 143
Endian, 59
ENIAC, 17
ENIGMA, 16
Enterprise, Sun, 570-571
Entry point, 511
Environmental subsystem, Windows NT, 453
EPIC (see Explicitly Parallel
Instruction Computing)
EPROM (see Erasable PROM)
Erasable PROM, 153, 154
Error-correcting code, 61-64
Escape code, 327
Estridge, Philip, 23-24
Ethernet, 595-596
Evolution of computers, 8-13
Excess notation, 638
Exe file, 506
Executable binary program, 484, 506
Executive, Windows NT, 452
Expanding opcode, 325-327
Explicit linking, 518
Explicitly parallel instruction computing, 391-393
Exponent, 644
Extended data output memory, 152-153
Extended IDE disk, 74
Extended ISA bus, 91, 183
External fragmentation, 419
External reference, 509
External symbol, 512
F
False sharing, 603
Fanout, 532
Fast page mode memory, 152
FAT (see File Allocation Table)
Fat tree network, 534
Fetch-decode-execute cycle, 42, 204
Fetch/decode unit, Pentium II, 285-286
Fiber, 474
FIFO (see First-In First-Out algorithm)
File, 430-431
File allocation table, 465
File descriptor, 459
File index, 432
File system, Windows NT, 452
Filter, 461
Fine-grained parallelism, 525
Finite state machine
branch prediction, 274-275
instruction fetch unit, 250-251
Finite-precision number, 631-633
First fit algorithm, 420
First-generation computers, 16-19
First-in first-out algorithm, 413
Flags register, 310
Flash memory, 153-154
Flat panel display, 94-95
Flip-flop, 143-145
octal, 147
Floating-point numbers, 643-651
Floppy disk, 73
Flow of control, ISA level, 370-383
Flow of control
procedures, 372-376
sequential, 371
Flynn's taxonomy, 551-553
FORTRAN, 9-10
FORTRAN monitor system, 10-11
Forward reference problem, 499
Fourth-generation computers, 23-24
FPM memory (see Memory, Fast
Page Mode)
Fraction, 644
Fragmentation
external, 419
internal, 414-415
Frame, CD-ROM, 82
Frame pointer, 312
Free list, 433
Free page, 457
Frequency modulation, 107
Frequency shift keying, 107
FSM (see Finite State Machine)
Full adder, 136-137
Full-duplex transmission, 108
Full handshake, 164
Full interconnect, 534
G
Gamut, 105
Garbage collector, 317
Gate, 5, 117-127
Gate delay, 129
GDT (see Global Descriptor Table)
Gigaplane-XB, 570
GigaRing, 590
Global descriptor table, 421
Globe, 608-609
Goto, MAL, 230-232
GOTO IJVM instruction, 222, 223, 240-241
Grain size, 525
Granularity of parallelism, 547-548
Graphical user interface, 449
Graphics device interface, Windows NT, 453
Green book, 83
Grid network, 534
GUI (see Graphical User Interface)
H
H register, 205, 228-229
Half adder, 135-136
Half-duplex transmission, 108
Halftone screen frequency, 104
Halftoning, 104
Hamming code, 62-64
Hamming distance, 61
Handle, 454
Hardware, 8
Hardware abstraction layer, 451
Hardware DSM, 574
Harvard architecture, 67
Hash coding, 506
Hazard, 258
Head-of-line blocking, 537
Headless workstation, 593
Heap, 317
Hexadecimal number, 633
High-level language, 7
Hit ratio, 66
Hoisting, code, 281
Host library, 519
Hub, 596
Hypercube, network, 534
I
I-node, 463
I/O (see Input/Output)
I/O instructions, 356-359
I/O manager, Windows NT, 452
IA-32, 285, 311
IA-64, 388-397
bundle, 392
EPIC model, 391-393
predication, 393-395
speculative load, 395-396
IADD IJVM instruction, 222, 223, 233, 236-237
IAS machine, 17
IBM 360, 21-22, 23
IBM 701, 19
IBM 704, 19
IBM 709, 10
IBM 801, 46
IBM 1401, 21
IBM 7094, 14, 20, 21, 23
IBM Corporation, 18-19, 20, 21
IBM PC
bus, 183
origin, 24
IBM PS/2, 182-183
IC (see Integrated Circuit)
IDE disk, 73-75
IEEE floating-point standard 754, 646-650
IF_ICMPEQ IJVM instruction, 222, 223,242
IFEQ IJVM instruction, 222, 223, 242
IFLT IJVM instruction, 222, 223, 242
IFU (see Instruction Fetch Unit)
IINC IJVM instruction, 222, 240
IJVM, 203-213, 218-227
constant pool, 220
control signal, 211-213
data path, 204-210
instruction set, 222-226
Java code, 226-227
local variable frame
memory model, 220-222
memory operation, 209-210
method area, 221
Mic-1 implementation, 232-243
Mic-2 implementation, 253-255
Mic-3 implementation, 253-260
Mic-4 implementation, 260-264
IJVM (continued)
operand stack, 221
stack, 218-220
timing, 207-209
ILC (see Instruction Location Counter)
ILLIAC, 17
ILLIAC IV, 53-54, 554
ILOAD IJVM instruction, 222, 237
Immediate addressing, 334
Immediate file, 469
Immediate operand, 334
Implicit linking, 518
Import library, 518
Indexed addressing, 336-338
Indexed color, 97
Indirect block, 464
Industry standard architecture, 91
Infix notation, 338
Initiator, PCI bus, 185
Ink, color printer, 105
Inkjet printer, 102
Input buffering, 537
Input/output, 89-112
Instruction execution, 42-45
Instruction fetch unit, 249-252
instruction folding, picoJava II, 294-296
Instruction formats
design criteria, 322-324
ISA level, 322-332
Pentium II, 327-328
Instruction location counter, 499
Instruction register, 40
Instruction set architecture, 6
Instruction set architecture level, 6
Instruction sets, comparison, 369-370
Instruction types, ISA level, 348-370
Instructions
comparisons and branches, 352-353
movement, 348-349
operations, 349-350
I/O, 356-359
control, 354-355
operations, 350-352
Pentium II, 359-362
picoJava II, 364-369
procedure calls, 353-354
Integer unit, 33
Integrated Circuit, 128-129
use in computers, 21-23
Integrated drive electronics disk, 73-75
Integrated services digital network, 108-109
Intel 4004, 29, 30
Intel 8008, 29, 30
Intel 8080, 29, 30
Intel 8086, 29, 30
Intel 8088, 29, 30
Intel 8255A, 194-195
Intel 8259A, 169-170
Intel 80286, 30, 30
Intel 80386, 30, 30
Intel 80486, 30, 30
Intel IA-64, 388-397
Intel Corporation, 29
Intel Pentium II (see Pentium II)
Intel/Sandia Option Red, 590-592
Intel x86 (see also Pentium II, IA-64), 29-31
Interconnection network, 530-532
bisection bandwidth, 532
switching, 535-538
topology, 532-535
off-the-shelf, 595-598
Interleaved, 573
Internal fragmentation, 414-415
Interpretation, 2
Interpreter, 2, 42-43
Interrupt, 90, 379-383
imprecise, 279
precise, 279
transparent, 381
Interrupt handler, 90
Interrupt service routine, 380-383
Interrupt vector, 169, 380
Intersector gap, 71
Invalidate strategy, 566
Inversion bubble, 119
Inverter, 119
Inverting buffer, 149
INVOKEVIRTUAL IJVM instruction,
222-225, 242-243
IOR IJVM instruction, 222, 223, 237
IQ-Link board, 581
IR (see Instruction register)
IRETURN IJVM instruction, 222, 223,
225-226, 242-243
ISA (see Industry Standard Architecture)
ISA (see Instruction Set Architecture)
ISA bus, 181-183
ISA level, 6, 303-402
Addressing, 342-347
data types, 318-321
flow of control, 370-383
instruction formats, 322-332
instruction types, 348-370
memory models, 307-309
overview, 305-318
properties, 305-307
ISDN (see Integrated Services Digital Network)
ISTORE IJVM instruction, 222, 223, 237
ISUB IJVM instruction, 222, 223, 237
IU, (see Integer Unit)
J
Java-to-IJVM translation, 226-227
Java virtual machine, 34-35
addressing modes, 346-347
data types, 321
instruction formats, 330-332
instructions, 364-368
overview, 317-318
towers of Hanoi, 386-389
JIT compiler (see Just In Time compiler)
Jobs, Steve, 23
JOHNIAC, 17
Joy, Bill, 32
Jump instruction (see Branch instruction)
Just in time compiler, 35
JVM (see Java Virtual machine)
K
Kernel mode, 307
Kestrel, 591
Key, file index, 432
Keyboard, 92
Khosla, Vinod, 32
L
Land, 80
Language, machine, 1
Laser printer, 102-104
Latch, 141-143
Latency, 51
Latency, rotational, 71
Latency hiding, 544-545
Latin-1, 111
Layer, 3
LBA (see Logical Block Addressing)
LCD (see Liquid Crystal Display)
LDC_W IJVM instruction, 222, 240
LDT (see Local Descriptor Table)
Least recently used algorithm, 269, 412-413
LED (see Light Emitting Diode)
Legacy bus, 170
Level, 2-4
Level 2 cache, 265
Level triggered versus edge triggered, 144
Light emitting diode, 100
Lightweight process, 547
Linda, 604-606
Line card, 596
Lines per inch, 104
Linear address, 423
Link system call, 461
Linkage editor, 506
Linkage segment, 515
Linker, 506
Linker, tasks, 508-511
Linking, 506-519
MULTICS, 515-516
UNIX, 519
Windows, 517-518
Linking loader, 506
Liquid crystal display, 94-95
Literal, 501
Little endian, 59
Load/store architecture, 48, 316
Local descriptor table, 421
Local memory table, 582
Local variable frame, 218, 220
Local variable pointer, 205, 221, 224, 232
Locality principle, 66
Logic circuit, 128-141
Logical block addressing, 74
Logical record, 431
Loop control instruction, 354-355
Loosely coupled system, 525
Lovelace, Ada, 15
LPI (see Lines Per Inch)
LRU (see Least Recently Used algorithm)
LRU (see Least Recently Used algorithm)
LV (see Local Variable pointer)
M
Machine language, 1
Macro, 494-498
call, 494
definition, 494
expansion, 494
implementation, 498
parameter, 496
Macroarchitecture, 218
Magnetic disk, 70-80
Mailslot, 475
Mainframe, 28
MAL (see Micro Assembly Language)
MANIAC
Mantissa, 644
MAR (see Memory Address Register)
Mask, 349
MASM, 488
pseudoinstructions, 491-493
Massively parallel processor, 553, 587-592
Master, bus, 158
Master file table, 469
Matrix printer, 101-102
Mauchley, John, 16-17
MBR (see Memory Buffer Register)
McNealy, Scott, 32
MDR (see Memory Data Register)
Memory, 56-68, 141-154
dynamic RAM, 152, 154
EDO, 152-153
EEPROM, 152, 154
EPROM, 153, 154
flash, 153-154
FPM, 152
primary, 56-68
Memory (continued)
PROM, 153, 154
random access, 152-154
ROM, 153, 154
secondary, 68-88
static RAM, 152, 154
Memory address, 57-58
Memory address register, 209-211
Memory buffer register, 209-212,
232, 238, 250-252
Memory chip, 150-152
Memory data register, 209-211
Memory hierarchy, 69-70
Memory management unit, 409
Memory map, 406
Memory-mapped I/O, 195-197
Memory organization, 146-150
Memory packaging, 67-68
Memory refresh, 152
Memory semantics, 559-563
processor consistency, 561-562
release consistency, 563
sequential consistency, 560-561
strict consistency, 560
Merced (see IA-64)
Mesh network, 534
MESI cache protocol, 568-569
Message-passing interface, 600-601
Message queue, 471
Method area, 221
Method, 354
Message passing, 598-601
MFT (see Master File Table)
Mic-1, 213-252
data path, 214
IJVM implementation, 232-243
implementation, 232-243
microprogram, 234-236
optimizing, 243-252
Mic-2, 252-255
data path, 252
microprogram, 253-255
prefetching, 253
Mic-3, 253-260
data path, 256
pipeline, 253-260
Mic-4, 260-264
data path, 261
Mickey, 101
Micro assembly language, 227-232
Micro-operation, 262
Microarchitecture
Pentium II, 283-288, 296-298
picojava II, 291-298
Microarchitecture level, 5, 203-302
Microarchitecture level, design, 243-264
Microinstruction, 45, 211-213
Microinstruction notation, 227-232
Microinstruction register, 215
MicroJava 701
chip-level view, 180-181
introduction, 35-36
Microkernel, Windows NT, 452
Microprogram, 6, 11-13
Microprogram counter, 215
Microprogramming, 8-9
Microsoft, 24
Microstep, 257
Milestones in computer architecture, 13-24
MIMD computer, 551-553
MIPS (acronym), 48
MIPS (chip), 46
MIR (see MicroInstruction Register)
MISD computer, 551-552
Miss ratio, 66
MMU (see Memory Management Unit)
MMX (see Multimedia Extensions)
Modem, 98
Modulation, 106-107
amplitude, 106-107
frequency, 107
phase, 107
Monadic instructions, 350-352
Monitor, 93
Moore, Gordon, 25, 29
Moore's law, 25
MOS, 120
Motherboard, 89
Motif, 449
Motorola 68000, 45
Mouse, 99
MPC (see MicroProgram Counter)
MPI (see Message Passing Interface)
MPP (see Massively Parallel Processor)
Multicasting, 550
Multicomputer, 56, 527, 552-553, 586-609
communication software, 598-601
COW, 592-598
Cray T3E, 589-590
MPI, 600-601
NOW, 592-598
Option Red, 590-592
PVM, 599-600
scalable, 529
scheduling, 593-595
MULTICS
development, 487
dynamic linking, 515-516
virtual memory, 420-421
Multilevel machine, 4-7
Multimedia extensions, 30
Multiplexed bus, 160
Multiplexer, 130
Multiprocessor, 55, 526-530, 559-586
bus-based UMA, 564-569
crossbar, 569-571
DASH, 577-580
multistage, 571-573
NUMA, 573-585
NUMA-Q, 581-585
snooping, 564-569
Multiprogramming, 22
Multisession CD-ROM, 85
Multistage switching network, 571-573
Multithreading, 544
Mutex, 473
Mutual exclusion, 550
Myhrvold, Nathan, 26
Myrinet, 597-598
N
N-way set-associative cache, 269
NaN (see Not A Number)
Nathan's first law of software, 26
NC-NUMA (see NonCoherent NUMA)
Negated signal, 151
Negative binary numbers, 637-640
Negative logic, 127
Network interface chip, 591
Network of workstations, 28, 553, 592-593
Nibble, 360
NIC (see Network Interface Chip)
No remote memory access, 553
Nonblocking network, 570
Noncoherent NUMA, 574
Noninverting buffer, 149
Nonuniform memory access, 553, 573-585
NOP IJVM instruction, 222, 236
NORMA (see NO Remote Memory Access)
Normalized, 646
Not a number, 650
NOW (see Network of Workstations)
Noyce, Robert, 21, 29
NT file system, 465
NTFS (see NT File System)
NUMA (see NonUniform Memory Access)
NUMA-Q multiprocessor, 581-585
O
Obj file, 506
Object manager, Windows NT, 452
Object module, 511-512
Object program, 484
OC-12, 596
Octal radix, 633
Off-line storage, 435
Olsen, Kenneth, 19
Omega network, 572
Omnibus, 19-20
On-line storage, 435
One's complement, 637
OPC register, 205, 232
Opcode, 204
Open collector, 158
Operand stack, 219-221, 226-227
Operating system, 9-11, 403
Operating system machine level, 6, 403-482
Operation code, 204
Option Blue, 591
Option Red, 590-592
Option White, 591
Orange book, 84
Orca, 606-608
Orthogonality of opcodes and
addressing, 342-344
Out-of-order execution, 276-281
Output buffering, 537
overflow error, 644
Overlay, 405
P
Packet, 531
Page, 406
Page directory, 423
Page fault, 409
Page frame, 408
Page replacement policy, 412-414
Page scanner, 575
Page size, 414-415
Page table, 406
Paging, 405-407
implementation, 407-409
Paradigm, computational, 548-549
Parallel computer
design issues, 524-553
performance, 539-545
software, 545-546, 598-609
taxonomy, 551-553
Parallel I/O chip, 194-195
Parallel processing, 436-445
Parallel virtual machine, 599-600
Parallelism
coarse-grained, 525
fine-grained, 525
granularity, 547-548
instruction-level, 49-53
processor-level, 53-56
Parity bit, 61
Partial address decoding, 197
Pascal, Blaise, 13
Pass, assembler, 499
Passive matrix display, 94
Path, 461
Path length, 244
reducing, 245-252
PC (see Program Counter)
PCI bus (see Peripheral Component
Interconnect bus)
PDP-1, 19
PDP-8, 19
Pentium II
addressing modes, 344-346
bus transaction, 174-175
chip-level overview, 170-175
data types, 320
dispatch/execute unit, 286-287
fetch/decode unit, 285-286
instruction formats, 327-328
instructions, 359-362
introduction, 29-31
ISA level overview, 311-313
microarchitecture, 283-288, 296-298
packaging, 171
pinout, 172-174
pipelined bus, 174-175
power management, 171-172
real mode, 311
registers, 312-313
retire unit, 287-288
towers of Hanoi, 384-385
virtual 8086 mode, 312
virtual memory, 421-426
Perfect shuffle, 572
Performance of parallel computers
achieving, 543-545
Amdahl's law, 541-542
hardware metrics, 539-541
latency hiding, 544-545
scalability, 543-544
software metrics, 541-543
improving, 264-283
Peripheral component interconnect
bus, 91, 183-189
signals, 187-189
transactions, 189
183-189
Phase modulation, 107
Physical address space, 406
PicoJava I design, 35
PicoJava II design
chip-level view, 179-181
dribbling, 293
folding, 294-296
instruction folding, 294-296
instructions, 364-369
introduction, 35
JVM addressing modes, 346-347
JVM data types, 321
PicoJava II design (continued)
JVM instruction formats, 330-332
JVM ISA level overview, 317-318
microarchitecture, 291-298
pipeline, 293-294
towers of Hanoi, 386-389
Pigment-based ink, 105
Pinout, 154
PIO chip, 194-195
Pipe, 470
Pipeline, 49, 548
Mic-3, 253-260
Mic-4, 260-264
Pentium, 51-52
picojava II, 293-294
Pipeline stage, 49
Pipeline stall, 272
Pit, 80
Pixel, 96
PLA (see Programmable Logic Array)
Point-to-point message passing, 550
Pointer, 335
Poison bit, 283
Polish notation, 338-342
POP IJVM instruction, 222, 223, 233, 237
Position independent code, 515
Positive logic, 127
POSIX, 447
POSIX subsystem, Windows NT, 453
Postfix notation, 338
Preamble, 70
Predication, 393-395
Prefetch buffer, 49
Prefetching, 544
Prefix byte, 239, 327, 360
Present/absent bit, 409
Print engine, 103
Printer, 101-106
color, 104-106
CYMK, 104
dye sublimation, 106
inkjet, 102
laser, 102-104
matrix, 101-102
monochrome, 101-104
wax, 106
Procedure, 372-376
Procedure call instruction, 353-354
Procedure epilog, 375
Procedure prolog, 375
Process and thread manager, Windows NT, 452
Process creation, 437
Process management
UNIX, 470-473
Windows NT, 473-476
Process synchronization, semaphores, 442-445
Processor, 39-56
Processor bandwidth, 51
Processor consistency, 561
Producer-consumer problem, 438-445
Program, 1
Program counter, 40, 205, 224
Program status word, 310
Pentium II, 425
Programmable logic array, 132
Programmable ROM, 153, 154
Programmed I/O, 356
PROM (see Programmable ROM)
Pseudoinstruction, 491
PSW (see Program Status Word)
Pthreads, 472
PVM (see Parallel Virtual Machine)
Q
Quad board, 581
Queueing unit, 262
R
Race condition, 438-442
Radix, 633
Radix conversion, 635-637
Radix number system, 633-634
RAID, 76-80
RAM (see Random Access Memory)
Random access memory, 152-154
dynamic RAM, 152
static RAM, 152
Raster scan, 93
RAW dependence, 258
Read only memory, 153, 154
Recursion, 354
Recursive procedure, 372
Red book, 80
Reduced instruction set computer, 24, 46-53
design principles, 47-49
versus CISC, 46-47
Reed-Solomon code, 71
Register, 5, 145-146
ISA level, 309-310
Register addressing, 334-335
Register indirect addressing, 335-336
Register mode, 334
Register renaming, 280-281
Register windows, 315-316
Relative error, 645
Release consistency, 563
Relocation, dynamic, 512-515
Relocation constant, 509
Relocation problem, 508
Reorder buffer, 284
Replicated worker paradigm, 548, 606
Reserved page, 457
Retire unit, Pentium II, 287-280
Reverse Polish notation, 338-342
Ring network, 534
Ripple carry adder, 137
RISC (see Reduced Instruction Set Computer)
ROB (see ReOrder Buffer)
ROM (see Read Only Memory)
Root directory, 461
Root hub, 191
Rotational latency, 71
Rounding, 645
Routing algorithms, 538-539
adaptive, 538
dimensional, 538
dynamic, 538
static, 538
RS-232-C terminal, 98-99
S
SBus, 177
Scalable coherent interface, 581-585
Scalable processor architecture, 32
Scalable system, 543
Scale, index, base, 328, 345-346
Scheduling, multicomputer, 593-595
SCI (see Scalable Coherent Interface)
Scoreboard, 277
SCSI (see Small Computer System Interface)
SDRAM (see Synchronous DRAM)
SEC (see Single Edge Cartridge)
Second-generation computers, 19-21
Sector, 70
Security descriptor, 468
Security ID, 468
Security manager, Windows NT, 453
Seek, 71
Segment, 416-418
Segmentation, 415-418
best fit, 420
first fit, 420
implementation, 418-421
Self-modifying program, 336
Semantics of memory (see Memory semantics)
Semaphore, 442-445
Sequencer, 213
Sequent NUMA-Q multiprocessor, 581-585
Sequential consistency, 560
Session, CD-ROM, 85
Set-associative cache, 269-270
Shared library, 519
Shared memory, application level, 601-609
Shared memory system (see Multiprocessor)
Shell, 449, 589
SIB (see Scale, Index, Base)
SID (see Security ID)
Sign extension, 210
Signed magnitude, 637
Significand, 648
SIMD computer, 551-552, 554-559
SIMM (see Single Inline Memory Module)
Simple COMA, 586
Simplex transmission, 108
Single edge cartridge, 171
Single inline memory module, 68
Single large expensive disk, 76
Single program multiple data, 548
SISD computer, 551
Skew, 536
Slave, bus, 158
SLED (see Single Large Expensive Disk)
Small computer system interface, 75-76
Small outline dimm, 68
SMP (see Symmetric MultiProcessor)
Snooping cache, 564-569
Snoopy cache, 564-569
SO-DIMM (see Small outline DIMM)
Socket, 447
Software for parallel computer, 545-546
communication, 598-609
scheduling, 593-595
Solaris, 447
Solid ink printer, 105
Source language, 483
Source routing, 538
SP (see Stack Pointer)
SPARC, 32
Spatial locality, 266
Speculative execution, 281-283
Speculative load, 395-396
Split cache, 67, 265
SPMD (see Single Program Multiple Data)
SR latch, 141-142
SRAM (see Static RAM)
Stack, 218-219
Stack addressing, 338-341
Stack pointer, 205, 218-221, 224
Stale data, 565
Stall, pipeline, 258, 272
Standard error, 461
Standard input, 461
Standard output, 461
Standardization, 306
Star network, 534
State, machine, 204
State, finite state machine, 250
Static RAM, 152, 154
Static routing, 538
Stibbitz, George, 15-16
Storage, 56
Store (see Memory)
Store-and-forward packet switching, 536
Stream, 448
Strict consistency, 560
Striping, 77
Strobe, 143
Structured computer organization, 2-4
Subroutine, 353
Sun Enterprise 10000, 570-571
Sun Microsystems, 32-33
Supercomputer, 21, 28
Cray-1, 557-559
Superscalar architecture, 52
Superuser, 463
Supervisor call, 11
SWAP IJVM instruction, 222, 223, 237, 257-259
Switched Ethernet, 596
Switching algebra, 120
Switching network, 535-538
Symbol table, 499
Symmetric multiprocessor, 559, 564-573
Synchronization primitive, 550-551
Synchronous bus, 160-163
Synchronous DRAM, 153
Synchronous message passing, 598
System bus, 157
System call, 11, 403
UNIX, 459-465
System interface, 453
System services, Windows NT, 453
Systems programmer, 7
T
Target, PCI bus, 185
Target language, 483
Target library, 519
Task bag, 606
Task farm, 548
TAT-12/13, 26
Taxonomy of parallel computers, 551-553
Template, 605
Temporal locality, 266
Terminal, 91-99
Third-generation computers, 21-23
Thrashing, 414
Thread, 547
Java, 439
UNIX, 471-473
Tightly-coupled system, 526
Timesharing system, 11
TLB (see Translation Lookaside Buffer)
Top of stack register, 205, 232
Topology, 532-535
TOS (see Top Of Stack register)
Towers of Hanoi, 372-376, 383-388
Pentium II, 384-385
picoJava II, 386-389
Track, 70
Transaction, bus, 174
PCI bus, 189
Transistor, 19-21
bipolar, 118-119
MOS, 120
Transistor-transistor logic, 120
Transition, finite state machine, 250
Translation, 2
Translation lookaside buffer, 427
TLB miss, 427
Translation storage buffer, 427-428
Translation table, 428
Translator, 483
Transparent interrupt, 381
Trap, 379
Trap handler, 379
Tree network, 534
Tri-state device, 149
Triple indirect block, 464
True dependence, 258
Truth table, 120
TSB (see Translation Storage Buffer)
TTL (see Transistor-Transistor Logic)
Tuning, program, 486
Tuple, 604
Tuple space, 604
Twisted nematic, 94
Two-pass translator, 499
Two's complement, 637
TX-0, 19
U
U pipeline, 51
UART (see Universal Asynchronous
Receiver Transmitter)
Ultra port architecture, 177
addressing modes, 346
chip-level view, 176-179
data buffer, 177
data types, 321
instruction formats, 328-330
instructions, 362-364
introduction, 31-34
ISA level overview, 313-316
microarchitecture, 288-291, 296-298
pipeline, 290-291
register windows, 315-316
towers of Hanoi, 384-387
virtual memory, 426-428
UMA (see Uniform Memory Access)
Underflow error, 645
UNICODE, 111-112
Unified cache, 67
Uniform memory access, 552
Universal asynchronous receiver
transmitter, 98, 193
Universal serial bus, 189-193
UNIX
Berkeley, 447
directory, 461-463
file descriptor, 459
file system implementation, 461-465
introduction, 446-449
pipe, 470
process management, 470-473
Solaris, 447
system calls, 459-465
System V, 447
thread, 471-473
virtual I/O, 459-465
UPA (see Ultra Port Architecture)
Update strategy, 566
USART, 193
USB (see Universal Serial Bus)
User mode, 307
V
V pipeline, 51
Vampire tap, 595
VAX, 45, 46
Vector, 555
Vector processor, 54, 555-559
Vector register, 54
Very large scale integration, 23
Video memory, 96
Video RAM, 97
Virtual 8086 mode, 312
Virtual address space, 406
Virtual cut through routing, 537
Virtual I/O, 429-436
implementation, 431-435
UNIX, 459-465
Windows NT, 465-470
Virtual machine, 2-4
Virtual memory, 404-429
compared to caching, 428-429
Pentium II, 421-426
UNIX, 455-456
Windows NT, 456-458
Virtual memory manager, Windows NT, 452
Virtual register, 218
Virtual topology, 601
Virtuous circle, 25
VIS (see Visual Instruction Set)
Visual instruction set, 33
VLSI (see Very Large Scale Integration)
Volume table of contents, 85
Von Neumann, John, 17-18
Von Neumann machine, 18, 41
VTOC (see Volume Table Of Contents)
W
Wait state, 161
WAR dependence (see Write After
Read dependence)
WAW dependence (see Write After
Write dependence)
Wax printer, 106
Weak consistency, 562
Whirlwind I, 18
WIDE IJVM instruction, 222, 239-240
WEIZAC, 17
Wilkes, Maurice, 44
Win32 API, 454
Win32 subsystem, 453
Winchester disk, 71
Window, 97
Windows 95, 449
Windows 98, 450
Windows New Technology, 450
Windows NT
file system, 469-470
graphics device interface, 452
hardware abstraction layer, 451
introduction, 450-455
microkernel, 452
object manager, 452
process management, 473-476
security, 452, 468
virtual I/O, 465-470
virtual memory manager, 452
Win32 API calls, 466-468
Wired-OR, 158
Word, 58
Working directory, 461
Working set model, 412
Wormhole routing, 537
Wozniak, 23
Write after read dependence, 278
Write after write dependence, 278
Write allocate cache, 270, 566
Write back cache, 270, 568
Write deferred cache, 270
Write once cache, 568
Write through cache, 270, 565
X
X Windows, 449
Xeon, 31
Y
Yellow book, 81
Z
Zilog Z8000, 45
Zuse, Konrad, 15